Verilog and Introduction to FPGA Workshop
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Mixed Signals is all set to make this year an efficacious one, starting off with a workshop on Verilog and introduction to FPGA on 10th Jan, 2021 for third & fourth year EC students on online mode. Time: 10:00-12:00 pm, 2:00-4:00 pm Registration closes at 11 pm tonight. In the end, we only regret the chances we didn't take. ✨
Name: Jacob Sabu
Field of Study: Electronics and Communication Engineering
College: MEC
Batch: 2015-2019
Company: OpenFive
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Jubi Cyriac: +91 90748 18845
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